A common problem of single-transistor FLASH memory designs is the so-called “over-erase” problem. An over-erased Flash memory cell is a Flash memory cell that has a very low threshold voltage Vt which is so low that, when that over-erased memory cell is accessed, the floating gate of that over-erased memory cell cannot be programmed to have a high enough Vt threshold voltage that it can be turned OFF to provide a logical output 0.
Conventional single-cell flash memory cells are programmed and erased using a procedure in which each memory bit cell is iteratively programmed and erased with a program/erase pulse in a short period of time and then verified. These two programming and verification steps are repeated until each memory cell has an acceptable Vt level.
In order to improve overall yield for a flash memory chip design, redundant columns are added to the chip to be available to replace a few defective bits in the chip and thereby transform a “bad” flash-memory chip with a few defective bits into a usable chip. During normal backend production testing, the regular memory cells of each block of a Flash memory device are cycled through a few erase cycles, including the corresponding preprogramming cycles, to verify proper operation of the regular memory cells of the Flash memory device. Only regular memory cells and those particular redundant cells that are currently being used to replace defective regular memory cells are preprogrammed, whereas unused redundant bits do not get preprogrammed. However, the same unused column redundant cells are erased together with regular cells in the bock being erased. Thus, during the course of backend testing, over-erased unused redundant bits that have not been preprogrammed can be present and those over-erased redundant memory cells can be subsequently used to replace defective regular memory cells. It is often difficult to recover a redundant memory cell from an over-erasure condition. Having erroneous data in redundant memory cells defeats the purpose for adding redundant columns to a Flash memory design.
One way of avoiding over-erasure in unused redundant cells is to add an additional preprogramming step in the backend testing that separately programs only unused redundant cells in a separate testing cycle. However, this approach is expensive because it adds more backend testing time. Additionally, a test program is needed to keep track of how many times each block has been erased and the unused redundant cell has been pulsed with a preprogramming pulse.
In conventional Flash memory designs, the column redundant granularity, or ratio of regular memory cells to column redundant cells is g:1. This means that each column redundant cell can replace only one of a certain set of g regular memory cells. Whenever one of the g regular memory cells is selected it will point to the same column redundant cell.